Implementation of SRAM for Embedded System Design

Author
Maheshwaran S, A.Amudha
Keywords
SOC; SRAM; DRAM; ATPG
Abstract
Embedded reminiscence performs a large position in digital structures functions due to the increase of the information dimension required by means of many of these applications, such as video games and conversation protocols. In addition, the ever-increasing hole between processor speed, most important memory, and bus pace (memory wall) creates a want for more on-chip reminiscence to hold the processor busy and amplify throughput. In addition to the expand of processor frequency, the integration of many cores or functional units on the identical chip, which is referred to as gadget on chip (SOC), requires larger memory size. Embedded reminiscence compromises greater than 50 p.c of the chip area and larger than eighty percent of transistor counts. Increased system variant due to science scaling and the want for excessive density reminiscence consequences in a huge assignment to meet the stringent necessities on performance, power, and yield. The SRAM is a one of the main roll of the embedded system memory.
References
[1] Wilkes, M. The memory gap and the future of high performance memories, ACM Computer Architecture News, vol. 29, March 2001, pp. 2–7. 2.
[2] Weste, N. and Harris, D. CMOS VLSI Design: A Circuits and Systems Perspective, AddisonWesley, 2005.
[3] G. Gerosa, S. Curtis, M. D’Addeo, B. J. B. Jiang, B. Kuttanna, F. Merchant, B. Patel, M. Taufi que, and H. Samarchi, A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-k; Metal Gate CMOS . 2008.
[4] Rabaey, J.Chandrakasan A.Nikolic B.; Digital Integrated Circuits (2nd Edition), Jan 2003.
[5] Kuhn, K. Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nano scale CMOS, Proc. IEDM, December 2007, pp. 471–474.
[6] Frank, A. Power-constrained CMOS scaling limits, IBM Journal of Research and Development, volume 46, December 2001, pp. 235–244.
[7] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Prolog to: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits, vol. 91, no. 2. IEEE, 2003, pp. 305–327.
[8] Wang; Bo Zheng; Bohr, M. A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply, IEEE J. Solid-State Circuits, volume 41,April 2006, pp. 146–152.
[9] K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, A 1.1GHz 12μA/Mb-Leakage RAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications, in IEEE ISSCC, February 2007, pp. 324–327

Received : 29 May 2022
Accepted : 17 September 2022
Published : 26 September 2022
DOI: 10.30726/esij/v9.i3.2022.93002

Download “Implementation-of-SRAM-for-Embedded-System-Design.pdf” Implementation-of-SRAM-for-Embedded-System-Design.pdf – Downloaded 12 times – 431 KB